利用移位寄存器74ls194构成一个八只彩灯控制电路
8 向彩色灯分为两个级别，每个级别有4 组，并用两个7 4 LS1 9 4 实现。两种花从中间到两侧都是对称的，毕竟，它们仍然从中间转到两侧。
否则它们都从右向左照亮，然后再关闭。
通过对模式的分析，我们可以看到两个 - 道路移动登记处之一7 4 LS1 9 4 功能应首先向左移动，然后向右移动，即首先S1 = 1 ，S0 = 0，然后成为S1 = 0，S0 = 1 第二个功能始终移动到质量质量上，以显示正确的动力流水。
输入ABCD以连接电源或接地，以指示流灯的原始状态。
输出QAQBQCQD连接4 个彩色灯。
时钟连接时钟。
清除在启动-up时高级设置，S1 S0首先设置高级别，并读取原始条件。
然后将其中一个（S0或S1 ）根据左移或右移将其设置为低水平。
它可以直接连接，因为实现可以将其视为与四个触发器一起连接的正时电路。
仅在计算驾驶功能后才能计算条件函数。
扩展信息：根据班次，通常将其分为三种类型：左移寄存器，右移寄存器和两个路移寄存器；根据移动数据的输入输出方法，它可以分为四个电路结构：串行输入系列输出，串行输入并行输出，并行输入序列输出和并行输入并行输出。
此外，某些移位寄存器还具有预设的形象函数，可以并行将数据放置在寄存器中。
换档寄存器可以进行数据升起和数据处理以实现串行并行相互数据转换，并且也可以连接到不同的偏移寄存器，例如环，扭圈计数器等。
参考来源：BAIDU Encyclopedia- Shift Register Memorial
74LS194可以用来干什么？
1 7 4 LS1 9 4 是最大3 6 MHz脉冲的4 位双侧变更寄存器。它的逻辑符号和销钉的调整如下图所示：其中：D0〜D1 是平行的入口端子； Q0〜Q3 是平行出口端子； SR右偏移系列入口终端； SL-LEFT SHIFT系列入口终端； S1 ，S0操作模式终端； - 是直接无条件的透明终端； CP-是时钟脉冲入口端子。
下表列出了7 4 LS1 9 4 模式控制和状态生产。
2 使用7 4 LS1 9 4 形成8 位移位寄存器。
该电路如下图所示。
将芯片（1 ）的Q3 ）连接到芯片SR（2 ），然后将芯片（2 ）的Q4 连接到芯片（1 ），形成8 位移位寄存器。
3 7 4 LS1 9 4 形成环形计数器。
如图3 所示，可以在其串行输入处再次产生变更寄存器的产生，并可以执行循环变化。
假设初始状态为Q3 Q2 Q1 Q0 = 1 000，在CP的作用下，将方式设置为右侧，并且输出状态为：上面图中的电路是一个计数器。
同时，出口末端的输出脉冲具有时间顺序，因此它们也可以用作顺序脉冲发生器。
常用门电路74系列器件
7 4 LS002 入口四个NAND门7 4 LS01 2 入口四个NAND门（OC）7 4 LS02 2 入口四个NAND GATE 7 4 LS03 2 入口四个NAND GATE（OC）7 4 LS04 六个逆变器7 4 LS05 SIGGILE电压门（OC）7 4 LS1 03 输入thne Nand门7 4 LS1 1 3 输入thne Nand门7 4 LS1 2 3 输入THNE NAND门（OC）7 4 LS1 3 4 输入双NAND门（SMIT TRIGGER）7 4 LS1 4 7 4 LS1 4 7 4 LS1 5 3 INTEM 1 5 3 INTEM 1 6 6 6 flaster/fluff tum bulds fulds aftne thnee fulds 1 6 octer can/oc）7 4 lots 1 4 lots 1 4 . OC） （OC，1 5 V）7 4 LS1 7 六个高压/驱动器输出缓冲区（OC，1 5 V）7 4 LS1 8 4 双NAND GATE 7 4 LS1 9 六逆变器（SMIT触发）入口。7 4 LS2 04 ENTRY NAND CATE NAND 7 4 LS2 1 4 DUGGA 7 4 LS2 2 DUAL NAND GATE ENTRY (OC) 7 4 LS2 3 INPUT DUAL EXPESTABLE NOR GATE 7 4 LS2 4 2 INPUT SQU NAND GATE (Trigger Smit) 7 4 LS2 5 4 DUAL NAND NAND (WITH GATE) 7 4 LS2 6 2 ENTROW ENTRANCE at the high level level and not bank transfer? NAND GATE 7 4 LS3 1 延迟电路7 4 LS3 2 2 四或门输入7 4 LS3 3 2 入口四个或非延迟器（开放收集器的输出）7 4 LS3 4 六个缓冲7 4 LS3 5 六个缓冲六个缓冲区（OC）7 4 LS3 6 2 进入四个或非buffer（gate）7 4 LS 3 7 4 LS3 7 2 fours3 7 2 fours3 7 2 apen apen apen apen apen apen apen apen apen apen apen apen apen apen apen apen apen apen apen apen apen apen apen apen apen。
Correct Four Open Colluffer) 7 4 LS3 9 2 Four or non-Buffer Entrance (Open Collectible Exit) 7 4 LS4 04 Double input or non-Buffer 7 4 LS4 1 BCD DECIMAL COUNTER 7 4 LS4 2 4 Wire-1 0 Decoder Line (BCD Input) 7 4 LS4 LS4 3 4 Wire-1 0 Decoder Line Decoder (entrance of the Lust 3 ) 7 4 LS4 4 Decoder电线1 0解码器）7 4 L。
Wire-1 0 Line Decoder (Lust 3 Code Input) 7 4 LS4 4 4 4 4 Wire-1 0 Line Decoder (Lust 3 Code Input) 7 4 LS4 4 INPUT S4 5 BCD-Decimal DeCoder/Driver 7 4 LS4 6 BCD-Seven-Segment Decoder/Driver 7 4 LS4 7 BCD-Seven-Segment Decoder/Driver 7 4 LS4 8 BCD-Seven-Segment解码器/驱动程序7 4 LS4 9 BCD-DECODING/驱动程序（OC）7 4 LS5 0，带有两个段（可以扩展一个闸门（可以扩展一个门）7 4 LS5 1 双重双2 -2 输入到两种方式2 -2 和Gate 7 4 LS5 1 DAIN 7 4 LS5 1 DUAL 3 -3 输入3 -3 7 4 LS5 3 Quad 2 -2 -3 -2 入口和O门（可扩展）7 4 LS5 4 Quad 2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -5 -5 -5 -5 -5 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -- 6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 - 6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 -6 Andor Gate 7 4 LS5 4 Quad 2 -3 -2 -进入Andor Gate 7 4 LS5 4 四轮驱动2 -2 -3 -2 进入Andor Gate 7 4 LS5 5 Quad 4 -4 入口Andor Gate（外部）7 4 LS6 0双Quad 7 4 LS6 1 Triple 3 3 入口和扩展7 4 LS6 2 Quad 7 4 LS6 2 Quad 2 -3 Quad 2 -3 Gate 6 3 6 3 Gate 6 3 6 3 Gate 6 3 6 3 Gate 7 4 les 7 4 les 7 4 les 7 4 l. 7 4 LS6 5 Quad 4 -2 -3 -2 Entry Andor Gate 7 4 LS7 0 Quad 4 -2 -2 -2 Input Andor Gate (OC) 7 4 LS7 0 Quad Junction Input Edge Especttro Jk Flip-Flop 7 4 LS7 1 INPUT R-SLOP-FLOP-FLOP 7 4 LS7 2 E GATE Flip-Flop 7 4 LS7 3 Master-Slave at Input R-Schiavi (with Clearing End) 7 4 LS7 4 FIGHTING DOUBTING D-TYPE TRIGGER (with Preset End and Clear End) 7 4 LS7 5 4 -Bit Bistable Latch 7 4 LS7 6 Dual J-K Trigger (with Preset End and Clear End) 7 4 LS7 7 4 -Bit Bistable Latch 7 4 LS7 8 Dual J-K Trigger (with Preset End, Common Clear End and Common Clock End) 7 4 LS8 0 GATED FULL ADDER 7 4 LS8 1 1 6 -BIT RAST MEQUE 7 4 LS8 2 2 -BIT BINARY ADDER COMPLETE (Quick Transport) 7 4 LS8 3 4 -BIT BINARY Full Adder (Quick Transport) 7 4 LS8 4 1 6 -Bit random access memory to Bindino 7 4 LS8 5 4 -Bit digital comparator 7 4 LS8 6 2 Input Gate Quad-Exor 7 4 LS8 7 Bit Bit Bit/Reverse Reverse Code/Oi 7 4 LS8 9 6 4 -Bit Reading/Scripture Memory 7 4 LS9 0 METER COUNTER 7 4 LS9 1 Shift Register 7 4 LS9 2 1 2 Counter Divisor (2 and 6 divisor) 7 4 LS9 3 4 BIT BINARY COURTTER 7 4 LS9 4 4 BIT SHIFT Register (Asyncronous) 7 4 LS9 5 4 BIT SHIFT Register (Parallel I) 7 4 LS 9 6 5 Masseggio.同步二进制报告的乘数7 4 LS1 00 OCTET双重稳定7 4 LS1 03 Trigggeggi Indeggio di Brigggers di brigggers duppio j-k Master-Slave（With With WithChiara Extrete) 7 4 LS1 06 TRIGGER on the negative dual-Slave Dual (with Trigger Master-Slave Dual Ende1 08 Trigger Master-Slave (with pre set, transparent, clock) 7 4 LS1 09 J-K double (with Assert, clear, positive) 7 4 LS1 1 0 with Gate J-K Master-Slave Trigger (with block) entry. 7 4 LS1 1 1 Double End-K-k double Trigger Double Trigger. 4 LS1 2 5 4 LS1 2 5 MULTABLE Multi-Vibrator (Tre States exit) 7 4 LS1 2 6 BUS Buffer Gate (Three States Output) 7 4 LS1 2 8 2 Driver Quad-on Line Driver Non Input line 7 4 LS1 3 1 3 -8 7 4 LS1 3 2 2 Quad-Non-Gate Entry (Trigger St) 7 4 LS1 3 3 1 3 Gate Nand Nand 7 4 LS1 3 2 2 Gate Quad-Exor-OR (OC) 7 4 LS1 3 7 8 -Select 1 Decoder Latch/Multiplexer 7 4 LS1 3 8 3 -8 Decoder Line/Multiplexer 7 4 LS1 3 9 Dugleded DgifeCimal/DRED DRIGLEDECIMA DRIFLEDED DRIFLEDED Counter/latch/decoder/driver 7 4 4 ls1 4 2 Counter/Latch/Decoder/Driver 7 4 4 LS1 4 0 Dual 4 Input and Driver Non Line 7 4 LS1 4 1 BCD Decoding/Driver 7 4 LS1 4 2 Counter/Latch Latch/Driver 7 4 4 LS1 4 5 4 -1 7 4 LS1 4 -Line-Line-Line Cocoder/Lecath 7 4 LS1 4 8 -3 -3 here is Deposi Ottole 7 4 LS1 5 01 6 Select 1 Data Selector (Output of the Reverse Complement) 7 4 LS1 5 1 8 Select 1 Data Selector (complementary output) 7 4 LS1 5 2 8 Select 1 Data Selector 7 4 LS1 5 3 Dual 4 Select 1 Data Selector/Multiplexser Data Selector 7 4 LS1 5 4 4 Line 7 4 LS1 5 5 .Code1 5 5 .Code1 5 5 .A6 LS1 5 5 .A6 LS1 5 5 .Fecoder 7 4 LS1 5 5 . Double decoder/Distributor 2 -4 (Output Totem) 7 4 LS1 5 6 Dual 2 -4 decoder/distributor (Open collection output) 7 4 LS1 5 7 Quad 2 Select 1 Data Selector/Multiplexer 7 4 LS1 5 8 Quad 2 Select 1 Data Selector (Reverse Exit) 7 4 LS1 6 0 can pre set the Bancronus Bancoronus Cereaus canoe Four -bit bite (and transparent transparent transparent 7 4 LS1 6 2 transparent meter can pre set the transparent BCD counter) 7 4 LS1 6 3 can pre set the four -bit binary counter (and transparent input exit to move movement to move bit of 8 -bit input. Ratio Multiplier 7 4 LS1 6 8 4 Bits Plus/Decimal Counter Synchronous (Decimal) 7 4 LS1 6 9 Reversible Binary Synchronous Binary 7 4 LS1 7 04 *4 Register Stack 7 4 LS1 7 1 Four D (with End of Cancellation) 7 4 LS1 7 2 1 6 compensation purpose) 7 4 LS1 7 4 6 D FLIP-FLOP FLIP-FLOP 7 4 LS1 7 5 QUAQ FLIP-FLOP 7 4 LS1 7 6 Decimal Preset Decimal against 7 4 LS1 7 7 2 -8 -1 6 Exadecimal Preset 7 4 LS1 7 8 Four-bit universal shift register 7 4 LS1 7 9 Four-bit turnover of 7 4 LS1 8 0 GENERATIONS VERIFICATED 7 4 LS1 7 8 CHECK AT FOUR Bit Universal verification Universal Shift Register 7 4 LS1 7 9 A four bits Universal Shift Register 7 4 LS1 8 0 GENERATIONS REALIFIER 1 ARITMETIC Unit/Function generator 7 4 LS1 8 2 FIRST GENERATOR OF TRANSPORT 7 4 LS1 8 3 Dual Reserve Carry Adder Complete 7 4 LS1 8 4 BCD Converter-Binary 7 4 LS1 8 5 Binary converter-BCD converter 7 4 LS1 9 0 Counter BCD, Binary) 7 4 LS1 9 1 9 1 Bincrous Reverse, Bindary Reverse, Bindary Reverse, Bindarous Reverse, Bingary Reversious, Bincroos 7 4 LS1 9 2 Synchish reversible meter (BCD, track) 7 4 LS1 9 3 同步反向反向反转（BCD，BCD，BCD，二进制）7 4 LS1 9 4 双向变化寄存器7 4 LS1 9 9 Stapper 7 4 LS2 1 02 -5 -5 -5 -1 十名支撑7 4 LS2 1 3 2 -N-1 1 0 N-1 0驱动器7 4 LS 2 2 2 1 trige duppoggio duppoggio duppoggio duppoggio 3 03 0 trige duppoggio duppoggio 3 4 4 ls2 3 0 7 4 LS2 3 1 OCTET3 BUS DRSER驱动器7 4 LS2 4 0 OCCET潜水员/线OCCETTUSE代码3 7 4 LS2 4 1 八个缓冲驱动器/线/Recepter线（原始代码的三个 - 状态输出）7 4 LS2 4 2 OTTO BUFFER/LINE DRINE/LINE LINE/LINE CERVEIVER 7 4 LS2 4 3 4 RECEVER 7 4 LS2 4 3 4 RECEVER 2 4 4 4 4 4 4 4 4 .线七七七七七七七七七七七七七七七七七七七七十七七七七七七七七十七。
（3 0V）7 4 LS2 4 7 4 解码/驾驶员 - 摩索调查解码/驱动器（1 5 V）7 4 LS2 4 8 4 解码线条调查/驱动程序/驱动器7 4 LS2 4 9 4 线 - segleggio解码/驱动器选择/驱动程序选择7 4 LS2 5 1 8 选择1 个数据选择器（三个州出口）7 4 L-lds loud loud loud loud loud tould Doupd doubl dould Double-double-ddoul根据选择器（三态输出）7 4 LS2 5 8 的7 4 LS2 5 7 数字1 选择1 个数据选择器（在三个状态下的反向代码）7 4 LS2 5 9 8 是Parallel 3 4 LS 2 4 LS 2 4 LS 2 4 LS的锁存3 4 LS2 6 5 输出。
7 4 LS2 6 6 2 输入Quad出生的大门（OC）7 4 LS2 7 02 04 8 位ROM（5 1 2 位字节Quad，OC，OC）7 4 LS2 7 1 2 04 8 BIIT ROM（2 5 6 BIT，OC，OC）7 4 LS2 7 3 1 0月7 4 LS2 7 4 4 *4 二进制多与优先级寄存器7 4 LS2 7 9 四r锁定7 4 LS2 8 09 位奇数/欧盟数字奇偶校验器/验证器7 4 LS2 8 1 7 4 LS2 8 3 4 位二进制二进制完整adder 7 4 LS2 9 0小数小数点柜台7 4 LS2 9 1 3 2 位模型7 4 LS模型7 4 LS型号7 4 LS2 9 4 L Bit Bit Sodel 7 4 L Bit Bit 7 4 L Bit 7 4 L Bit 7 4 L Bit Bit 7 4 L Bit Sybir 7 4 l Bit Sybiir 7 4 L bit 7 4 l bit 7 4 lit bit 7 4 l bit 7 4 l bit 7 4 l 4 位7 4 LS2 9 8 多路复用器输入四边形-2 （带门）7 4 LS2 9 9 州位状态状态选择7 4 LS-S-3 4 8 -3 第3 行4 -1 数据选择器（三个状态输出）7 4 LS3 5 4 8 数据/寄存器的多重寄存器7 4 LS-dodation/dodument dotufer dodument oftive 7 4 dogation/登记7 4 LS3 5 6 8 多路复用器/数据选择器/寄存器，总线输出，3 4 LS3 6 5 6 行3 6 LS3 6 5 6 驱动程序7 4 LS3 6 7 带有三个状态7 4 LS3 6 8 的六个相同的驱动程序缓冲区/线7 4 LS3 6 8 反向7 4 LS3 7 3 Otto-D Latch 7 4 LS3 7 4 触发Otto Dei（触发Triggs3 7 9 BITGS3 7 9 BITGS3 7 9 7 4 LS3 8 1 ARITHMETIC UNITHMET/FIRCONTATION 7 4 LLICTORTORTORATORATORATORATORATOR 7 4 LLS3 8 8 2 ARMERTAR 3 2 ARINT2 ARINT2 ARINT2 ARINT2 ARINT2 ARINT2 ARINT2 ARMEN 3 8 2 ARINITH8 2 2 7 4 LS3 8 4 8 Bits*1 Bit Bit Multiplier Complement 7 4 LS3 8 5 ADDER SERIALE/MULULOR SERIVE BIRY 7 4 LS3 8 6 2 ENTRANCE EXCLUSION OR OR EXCLUSION OR EXCLUSION OR OR OR OR Orit or EXCLUSIONS EXCLUSION 7 4 LS3 9 5 4 BITE REGISTER OF MONTAGLE 7 4 LS3 9 6 MEMORY REGISTER A 7 4 LS3 9 8 Quattro-2 Input Multi-Switch （双输出）7 4 LS3 9 9 4 -2 输入到四个2 （带门）7 4 LS4 2 2 单个单一单位可触发触发器7 4 LS4 2 3 双FLIP-FLOP 7 4 LS4 0总线3 个方向3 个方向7 4 LS4 4 1 ，开放式3 -exector 3 -exection 3 -exection 3 -extres 3 -extres 3 -exceiver 3 -extres 3 -exceiver 3 -extres Quardy 3 -extres 3 -extres Quardy 3 -extres Quards Quardy 3 -exceiver 7 4 ls3 9 9 4 -2 三个方向GG路，树州4 4 4 4 LS4 4 驱动器7 4 4 4 7 4 LS驱动器7 4 LS 7 4 LS在三个季节的三个stods 7 4 LSEDPUT输出，跨加工双向管理双向管理总线7 4 LS4 4 4 4 8 8 -3 -3 州线音乐会7 4 LS4 6 6 8 -3 的8 -3 线线的缓冲线线。
十进制仪表7 4 LS5 4 0缓冲液缓冲总线，带有三个8 位状态（逆）7 4 LS5 4 1 缓冲液缓冲总线，带有三个8 位7 4 LS5 8 9 状态，带有输入lachse的串行式移动以及8 位寄存器7 4 LS 5 4 LS 5 4 LS 5 4 LS。
8 -Bit Binary Counter With Output Register 7 4 LS5 9 4 8 -Bit Serial-In and Out Shift Register 7 4 LS5 9 5 8 -Bit Output Latch Shift Register 7 4 LS5 9 6 8 -Bit Serial in and out shift Register with Output Latch 7 4 LS5 9 7 8 -Bit Output Latch Shift Register 7 4 LS5 9 8 -Bit serial in and out shift direction with input lachch 7 4 ls5 9 9 8 -bit serial in and out shift register with output stop 7 4 LS6 04 Duppoggio dopp that 7 4 ls6 05 Duppoggio at 8 bit 7 4 LS6 06 DUPPGGIO Due A 8 Bit 7 4 LS6 07 DUPPORE Due that Bust 7 4 LS6 LS6 LS6 2 2 2 2 2 2 2 2 2 08 -BIT BUSCEVEVEVEVEVEVEVEVEVERS 7 4 LS6 2 3 8 -BIT BUS TRANSCEIVER 7 4 LS6 4 0 INVERED总线收发器（三州输出）7 4 LS6 4 1 In-Phase 8 -Bus Transcneiver, Open electrode set 7 4 ls6 4 2 in-phase 8 Bus Transceiver, Open Collector 7 4 LS6 4 3 8 -Bit Three-State Transmitter BUSCER 7 4 LS6 4 4 TRUTH INVERTING 8 BUS Transceiver, Open Collector 7 4 LS6 4 5 Trescus Tresto in-Fase 8 bus 8 -Fase 7 4 LS6 4 6 BUS BUS BIT, records 7 4 LS6 4 7 TranseCchio Bus OITO位，注册7 4 LS6 4 8 RANESCCULLA OLD BUS 7 4 LS6 5 2 Transoceiver 7 4 LS6 5 3 Inverte 8 Transceiver Bus, manifold open 7 4 LS6 5 4 Tresceiver in-fase 8 buses, manifold open 7 4 LS6 5 4 Bus Tresagno in phase 8 in phase 8 , manifold open 7 4 ls6 6 8 4 bit synchronous addition/sub-sub-eighty of synchronous addition 7 4 ls6 7 04 *4 Register Stack Stack Stack Stack Stack （三态）7 4 LS6 7 1 4 位进出班次7 4 LS6 7 7 2 4 位内移登记册7 4 LS6 7 3 1 6 -6 7 3 1 6 位平行输出记忆，1 6 位串行的串行串行内部内部内部内部内部内部内部内部内部内部内部的内部序列内部偏见，这些序列偏见，这些序列偏见，这些序列偏见，这些序列偏见，这些序列偏见的内部序列中的缩调内部序列中的内部序列中的内部内部。
二等间间均二等内部二等内部临界内串行内隔离内隔离间隔内隔离间隔内隔离内隔离内部隔离内二聚体内部的乳房内二等内部的间隔内乳腺内乳液内序列内部序列内部序列内部序列序列序列的，隔离内隔离内隔离内串行内隔离内隔离间隔离内隔离内隔离内隔离内隔离内部隔离内部内部内部内部内部内部隔离内二等内氏乳胶内二等内部二等隔离内二等内部二等内部二等内部隔离内综合内部杂种内综合内部内部次数序列序列序列序列序列，收集器）7 4 LS6 8 6 8 位数字比较器（OC Collection Ampaer）7 4 LS数字比较器（OC OPS6 LS数字输出比较）7 4 LS6 8 9 8 位数字比较器7 4 LS6 9 0同步十进制符号符号SKARMA SKARMA SKARMA SKARMA登记册 7 4 LS6 9 2 Synchronous Decimal Counter (Conversation Predefinito, Synconous 7 4 LS6 9 3 (Multiple Conversation) 7 4 LS6 9 2 Synchronous Decimal Counter (Syncroneus Clearus) Output) 7 4 LS6 9 6 Synchronic addition/subtraction Decimal Counter/Register (with Select, three -states output, directly clear) 7 4 ls6 9 7 Counter/Register (with conversion conversion Multipla, three -states output) 7 4 LS6 9 8 Counter/Register (with multiple conversion, three -states output) 7 4 LS6 9 9 Counter/Register (with multiple conversion, with multiple conversion, with multiple, with multiple conversion) with multiple conversion (with multiple conversion) CD4 001 4 NAND GATE NAND two CD4 002 CD4 006 with a 1 8 -bit CD4 007 CD4 007 CD4 007 CD4 007 CD4 007 CD4 007 添加CD4 01 3 转换和NAND DUPAD 4 1 3 DUPEP-FLOP CD4 01 3 CD4 01 3 CD4 01 3 DUPEP-FLOP CD4 01 3 的CD4 01 3 转换和NAND DUPAD 4 1 3 的CD4 009 CD4 009 cd4 009 CD4 01 4 8 -Bit Sympotic Sympathic Sincononous CD4 01 5 4 -bit 4 -bit CD4 01 6 CD4 01 6 CD4 01 6 SWITCH DIGITAL DIGTI-BIDIERNATIONAL CD4 01 7 1 0 Decimal Decimal Council CD4 01 8 CAPET 1 /n couunter CD4 01 9 4 E/O/O/O/O/O/or/or/or/or/or/or/or/or/or selection selection CD4 01 4 位位点CD4 02 1 8 位位静态静态输出CD4 02 2 解码8 -DETPUT CD4 0-DETPUT 8 -DETPUN 8 -RDECTPUN 8 -RDEPPED CD4 0-DETPUT。
CD4 02 3 Three Input Nand Gate CD4 02 4 7 Bit Bit Binary Pulse Counter CD4 02 5 Three Input Nand Gate CD4 02 6 Decimal/7 Segment decoding/Drive CD4 02 7 Set/reset Master-Slave Trigger CD 4 02 8 BCD Decimal Decoder CD4 02 9 4 Bits can be sockets Reversible Council CD4 03 0 Quad-Exclusive OR GATE CD4 03 1 6 4 BIT STATIC SHIFT REGISTER CD4 03 2 TRE ADDER SERIAL CD4 03 3 DECIMAL OBLE/7 SEGEMENT CD4 03 4 8 BIT STATIC SHIFT REGISTER CD4 03 5 4 BITS IN/OUT SHIFT REGISTER CD4 03 8 3 BIT Bit Adder Serial CD4 04 01 2 Bit Bit CD4 04 1 Four Original Code/Complement CD4 04 2 CD4 04 2 Quad D-Type Latch Non-R/s Counter CD4 04 4 .闩锁非R/S CD4 04 6 LOP LOP LOP CD4 04 7 多振动器一个状态尚未准备好单个状态CD4 04 8 可以扩展Eight input gate CD4 04 9 Six inverted phase buffer/converter CD4 05 0 CD4 05 0 CD4 05 1 CD4 05 1 CD4 05 1 CD4 05 2 with 8 channels 8 channels 8 channel channels conversion/distribution multi -channel CD4 05 6 7 LCD LCD Decoding/Drive Binary/Divide/Ozing CD4 06 3 4 -digit 4 -digit numerical comparator CD4 06 6 CD4 06 6 CD4 06 6 CD4 06 6 CD4 06 6 CD4 06 6 CD4 06 6 CD4 06 6 CD4 0 CD4 0入口。
或门CD4 07 1 四2 输入或门CD4 07 2 双四分之一输入或门CD4 07 3 输入和门CD4 07 7 5 3 3 输入和门CD4 07 6 4 位D型d型寄存器寄存器寄存器CD4 07 7 QUAD NAND NAND GAIN NAND GAIT Gate CD4 08 6 Expandable 2 Input and Gate CD4 09 3 Quad and Non-Smit Trigger CD4 09 4 8 BIT SHIFT/STORAGE BUS REGISTER CD4 09 6 3 INPUT J-K Trigger CD4 09 8 Dual Mondostable State Trigger CD4 09 9 8 -Bit Addressable Latch CD4 01 03 Synchronous Preset Subtrator CD4 01 06 Six Smit Trigger CD4 01 07 Dual 2 Inputs and非缓冲/驱动CD4 01 1 0计数/解码/锁存/GUIDA4 01 7 4 6 D触发CD4 01 7 5 4 D触发CD4 01 9 2 BCD预测可逆CD4 01 9 3 BININO PRESET PRESET PRESET PRESET BINILAL BINILAL BINILAL BINILAL BILIAMIBLIBLIBLE CD4 01 9 4 4 -BIT BIFASE SHIPH REMPHIS
74LS系列是由什么门电路组成的
类别：游戏>>电视游戏问题描述：设计电路时，您需要购买组件。老师说，电路图的北约门已集成到7 4 LS系列中。
我想问哪个门电路由此芯片组成。
帮助专家！呢呢分析：7 4 系列：7 4 LS00TL2 输入4 NAND GATE 7 4 LS01 TTL开放收集器2 输入4 NAND GATE 7 4 LS02 TL2 输入4 NAND GATE 7 4 LS03 TL打开收集器2 输入4 NAND GATE 7 4 LS04 TL 7 4 TL OPENER COLLECTOR 6 INVER 7 4 L 7 4 L OPEN OPEN OPEN OPEN OPEN类型。
集合6 -in-但相位高电压驱动器7 4 LS07 TL打开收集器6 相电压驱动器7 4 LS08 TL2 输入4 Annd Gate 7 4 LS09 TL打开收集器2 输入4 Annd Gate 7 4 LS1 0TL3 3 Nand Gate 7 4 LS1 07 TL带有7 4 LS1 07 TLS1 07 TL SLAFF SLAFF SLAFF 7 4 LS（1 09 ）。
清晰的抽水触发双J-K FLIP FLOP 7 4 LS1 1 TTL3 输入端子3 和GATE 7 4 LS1 1 2 TL Pre-Set负电极触发触发双J-K K-K Flip Flip Flip Flip Flip Flip Flip Flip Flip Flip Flip Flip Flip Flip Flip 3 Input 3 和Gate 7 4 LS1 2 1 TL Instemwater Instemwater Instewater Dairater Dairer。
7 4 LS1 2 3 TL双重再训练双重再培训机兄弟兄弟7 4 LS1 2 5 TL 3 状态输出高有效Quadbus缓冲栅极GATE 7 4 LS1 2 6 TL 3 低有效的四元缓冲仪7 4 LS1 3 TL4 输入双重缓冲栅极GATE 7 4 LS1 3 TL4 输入双重和非shcmit trigger trigger 7 4 LS1 3 2 TL2 Intigt fipt firign trigpe frigper trigper firigt firign frigt firtign trigp firign trigper 4 和非Schmitt触发7 4 LS1 1 3 3 TL1 3 输入端子NAND GATE 7 4 LS1 3 6 TL QUAD-OXCLUSIOS或GATE 7 4 LS1 3 8 TL3 -8 线解码器/restoration 7 4 LS1 3 9 TL双重解码器/RESTOR/RESTOR/RESTOR 7 4 LS1 4 T1 4 T1 4 T1 4 T1 4 T1 4 T1 4 TL 7 4 LLS1 4 LLS1 4 LLBCCDERS 7 4 LS1 5 0TL1 6 选择1 数据选择/多交换机7 4 LS1 5 1 5 1 TTL8 选择1 Data Setter 7 4 LS1 5 3 TL 4 SELET 1 选择7 4 LS1 5 4 TL4 TL4 LINE1 5 4 TL4 LINE。
Decoder 7 4 LS1 5 5 TL Totempol Output Decoder/Distributor 7 4 LS1 5 6 TL Opened Output Decoder/Allocation 7 4 LS1 5 7 TL Phase Output 4 2 -SELECT 1 Data Soldier 7 4 LS1 5 8 TTL Butter/Drication 7 4 ls1 6 0tl Preset BCD asynchronous Clear Counter 7 4 LS1 6 1 TL Preset 4 -BIT BINARY ASYNCHONOUS Clear Counter 7 4 LS1 6 2 TL Preset BCD Synchronous Clear Counter 7 4 LS1 6 3 TL Preset 4 -bit Binary Synchronous Clear Counter 7 4 LS1 6 4 TTL OCTETL OUTPUT Shift Register 7 4 LS1 6 5 TTL Oktop Parallel IN/Serial Exception Shift Register 7 4 LS1 6 6 TTL Out Parallel/Serial Soft Resist 7 4 LS1 6 6 TL OCTET IN/SERIAL OUTPUT SHIFF Output Shift Register 7 4 LS1 6 6 TL Ok IN 7 4 LS1 6 9 TL Binary 4 Bit Add/Desubtrant Synchonous Counthous Counte 7 4 LS1 7 TL Open OPENCER in Phase Buffer/Driver 7 4 LS1 7 0TL Output 4 × 4 Registers 7 4 LS1 7 3 TL 3 rd stage drant trantat drantat drantat. 7 4 LS1 7 4 TL with 7 4 LS1 7 4 TL with Common Clock and Common Clock Reset 6 D Flip Flop 7 4 LS1 7 5 TL and 4 DLip Flop 7 4 LS1 8 0TL9 -BIT Odd9 -Bit Odu/Number Creation/Provider 7 4 LS1 8 1 TL Arthmetic Logic Unit/Fundure Generator 7 4 LS1 8 5 TTL BINARD BINARD BINARD BINARD Binard Binarn。
7 4 LS1 9 0TTLBCD动机/DESUBTRANT计数器7 4 LS1 9 1 TTL二进制动机动机动机动机动机动机动机7 4 LS1 9 2 TL可以预先建立的BCD双重可逆可逆7 4 LS1 9 3 TL。
7 4 LS1 9 5 TL 4 位平行通道偏移寄存器7 4 LS1 9 6 TTL OBXAGE/双描述计数计数闩锁7 4 LS1 9 7 TL二进制二进制二进制latch/counter 7 4 LS2 0TL4 输入门7 4 LS2 1 TL4 输入GATE GATE 7 4 LS2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 TTL OPEN CILDIC 4 输入DEUL NANT DEUL NANT输出输出输出输出输出4 Intpect 4 Intpect 4 Intpect。
7 4 LS2 2 1 TL双/单位可振动器7 4 LS2 4 0TL编号8 3 -상태/라인라인라인드라이브드라이브7 4 LS2 4 1 TTL8 英寸在in-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-IN-7 4 LS2 4 3 TTTL 4 인치3 3 3 단계7 4 LS2 4 4 TTTTT8 개-3 3 3 3 3 3 3 단계의단계단계단계단계단계트랜스트랜스단계단계단계트랜스트랜스트랜스트랜스트랜스트랜스트랜스트랜스트랜스트랜스트랜스트랜스 7 4 LS2 4 5 TL 8 -in-in-The-STATE bus transceiver 7 4 ls2 4 7 ttlbcd-7 -segment 1 5 V output decoding/driver 7 4 LS2 4 8 TTLBCD —7 segment decoding/boost output driver 7 4 LS2 4 9 TLBCD —7 -segment Decoding/Open Driver 7 4 LS 2 5 1 Output 8 -Selection 1 Data Setter/Result 7 4 LS2 5 3 TL 3 状态输出双4 选择1 数据设置器/结果7 4 LS2 5 6 TL双重四位指定7 4 L S2 5 7 TL原始代码4 2 -Slect 7 4 LS2 5 8 TTTL 4 2 选择1 SELECT 1 SELECT 1 SELLECT 1 SELLECT 1 SELLECT 1 SELLECT 1 SELLECT 1 SELLECT 1 SELLECT 1 SELLECT 1 SELLECT 1 SELLECT 1 7 4 LS2 5 9 TTLS2 6 TTLS 2 009 TTTLS 2 009 TTLS 2 009 TTLS 2 009 TTLS 2 009 TTTLS 2 00 7 4 . 3 -- 3 --3 -- 3 --3 --3 -- 3 -- 3 -- 3 -- 3 --- 3 --- 3 -3 --- 3 -- 3 -- 3 .-- 3 --- 3 .-- 3 -- 3 .-- 3 --옥트옥트 입력입력고전압인터페이스고전압4 nand게이트7 4 LS2 6 0TL5 输入双门7 4 LS2 6 6 6 6 6 6 TL2 4 NAND GATE 7 4 LS2 7 TL3 输入3 NAND GATE 7 4 LS2 7 3 TT，带有4 LS2 7 9 TL 4 totpol s-ratts s-ratch 7 4 LS2 8 TRINION fit Bufffers 2 inig fulst for 7 4 LS2 9 0TL2 /5 位数计数器7 4 LS2 9 3 TL2 /8 -DIT四位二进制二进制反式7 4 LS2 9 5 TL四位数双向换档通用迁移寄移寄存器7 4 LS2 9 8 TL四输入四输入的多路复用存储储存开关7 4 LS2 9 9 9 9 9 9 9 9 9 T-STATE UNVISERALT八位端口码及其架子7 4 L终端7 4 L端口7 4 LL8 量表7 4 LS3 2 TL2 输入端子4 -凝聚力7 4 LS3 2 2 TL签名的扩展烟雾签名的早期8 位移位寄存器7 4 LS3 3 3 3 3 3 3 3 3 3 3 3 3 TL开放输出2 输入端子端子4 -AR NON-AR NON-AR NON-BUFFER 7 4 LS3 4 7 TTTLBCD-7 -7 -7 -SERGRED/驱动程序。
7 4 LS3 5 2 TL Dual 4 -SELECT 1 Data Setter/Restoration 7 4 4 LS3 3 TL Output 2 input Terminal 4 or Beabuff 7 4 LS3 4 7 TLBCD —7 Segent Decoder/Driver 7 4 LS3 5 2 TL Dual 4 -SELECT 1 Data Setter/Restoration 7 4 LS3 5 LS3 5 2 2 TL DULE SELERECENTOR 7 4 4 LS3 5 3 TL 3 -State Output Dual 4 -Selection 1 Data Soldier/Restoration 7 4 LS3 6 5 TTL Gate Activation 3 -State Output 3 -State Output 6 Line Driver 7 4 LS3 6 6 TL Gate Activation 3 Phase 3 Output 6 output 6 output 6 output 7 4 LS3 6 7 TL4 /2 Line 3 -State 6 Phase Line Driver 7 4 LS3 6 8 TL4 /2 Line Input 3 -State 6 Stage 6 Driver 7 4 LS3 7 7 TT 2 Input 4 和非BUDDHA 7 4 LS3 7 3 TL阶段3 7 4 L-2 阶段3 7 4 L-2 阶段3 7 4 LS中的3 7 4 L-2 阶段3 .3 7 4 LS3 7 5 TL 4 位VY稳定vy稳定LATCE LATCE LATCH 7 4 LS3 7 7 TL 7 4 LS3 7 7 TL单一latch latch 7 4 ls latch 7 4 ls latch 7 4 LS3 7 8 TLS 3 7 8 TLS COONSL常见常见常见常见常见常见常见常见常见常见常见常见的常见常见常见的常见常见7 9 . 7 4 LS3 8 TTT 2 输入4 和非数量7 4 LS 7 4 LS3 8 0T输出。
Multifunctional Resistor 7 4 LS3 9 0TL Open Output 2 Input 4 and Beabuffers 7 4 LS3 9 0TL DOUBLE DECIMAL COUNTER 7 4 LS3 9 3 TL Double 4 BIT BINARY COUN Soldier/Restoration 7 4 LS3 5 3 TL 3 State Output Dual 4 Select Data Soldier/Restore 7 4 LS3 6 5 TT LICE Input 3 -State Output 6 Line Driver 7 4 LS3 6 6 TTL Gate Activation 3 -State Output 6 Person Line Driver 7 4 LS3 6 7 TL4 /2 ENABUP INPUP INPUP INPUP INPUT 3 Station 7 4 LS3 6 8 TL4 /2 Line 3 Input 3 Status 6 Rotate Line Driver 7 4 LS3 7 7 TL Output 2 Input 4 and Beabuffers 7 4 LS3 7 3 TL 8 4 LS3 7 4 TTT 8 -DATCE 7 4 LS3 7 5 TT 4 -BIT BitBITSTEDLATER 7 4 LS3 7 7 TL single side output common activation 8 -d latch 7 4 LS3 7 8 TTL single side output common 6 -dimensional latch 7 4 LS3 7 9 TTL Bid-sided output common 4 -d latch 7 4 LS3 8 TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTL 7 4 LS3 8 TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT 7 4 L 7 4 L Common Common Common Common Common Common Common Common Common Common Common Common Common Common Common Common L open output 2 Input 4 and Non -Corruption 7 4 LS3 8 0TL Multifunctional Resist 7 4 LS3 9 TL Open Output 2 Input 4 and Beabuffers 7 4 LS3 9 0TTTT DOUBLE DECIMAL COUN Converter 7 4 LS4 4 7 TTLBCD —7 Segent Decoder/Driver 7 4 LS4 5 TTLBCD- Decimal Coderter/Driver 7 4 LS4 5 0TL1 6 : 1 multiplex Multiplexer 7 4 LS4 5 1 TTL 8 : 1 Multiplexer Multiplexer 7 4 LS4 5 3 TTTTTTTTTTT Effective Decoding/Driver 7 4 LS4 6 0TL 1 0-Bit Comparator 7 4 LS4 6 1 TL Ochattl 7 4 LS4 6 5 TL 3 Stage 2 in 3 Status 2 and ENABLE 8 Bus Burpers 7 4 L BUFER 7 4 L BUFER 7 4 L BUFER 7 4 L BUFFER. 3 个状态内部2 和启用8 个总线缓冲冲击7 4 LS4 6 8 TTL 3 -state逆变器2 启用终端8 -Booth Buffer 7 4 LS4 6 9 TL 2 -Way反击7 4 LS4 7 TLS4 7 TLS4 7 TLBCD - 7 段高效效率高效高效率高效率高效率/驱动程序7 4 LS4 8 TLS4 8 TLS4 8 TLS4 8 TLS4 8 TLS4 8 TLS4 8 TLBCD加路加速器加速端口加路 7 4 LS4 9 0TL DOUBLE DOUBLE DECIMAL COUN GATE 7 4 LS5 3 TL 3 Main Revers 7 4 LS 5 3 4 TL 3 -STATE 8 -D Latch 7 4 LS5 4 TL 4 Channel input and NATO GATE 7 4 LS5 4 0TL 8 -Bit 3 -Bit 3 -Bit 3 -Bit 3 -Bit Inverted Output Bus Purpers 7 4 LS5 5 5 TL4 Input 2 7 4 LS5 6 4 TL 8 -bit 3 状态逆转输出D Flip Flop 7 4 LS5 7 3 T 3 状态输出FLOP 7 4 LS5 7 4 TL 8 位3 状态输出Dflip-Flop 7 4 LS6 4 5 TL 3 语句8 Force Transfer。
7 4 LS6 7 0TL 3 -Status Output 4 × 4 Register Stack 7 4 LS7 3 TL Clear Matent Eaturgue Trigger J-K Flip Flop 7 4 LS7 4 TL Set Resetting Trigger Dual Dual D Flop 7 4 LS7 6 TL Preset Clear Dual J-K Flip Flap 7 4 LS8 3 TTTTTTTTTTTTTT FOUR-BIT BING BING BINGEN 7 4 LS8 5 TL 4 位数字比较器7 4 LS8 6 TL2 输入4 市政或门7 4 LS9 0TL 2 -7 4 LS9 5 TTTT 4 位平行输入和输出移位寄存器7 4 LS9 7 TTTL6 -PIT动机是参考。
